Despite advances in semiconductor processing and manufacturing technology, integrated circuits are manufactured with errors. Unfortunately, a single error can render an integrated circuit unusable. Accordingly, various techniques to identify faults in integrated circuits have been developed.
Two leading strategies used to test integrated circuit logic are automatic test pattern generation (ATPG) and logic built-in self-test (LBIST). ATPG works by applying patterns from an external tester and observing the results. BIST works by sending out test patterns generated by a pseudorandom pattern generator along scan chains and then collecting the responses in a multiple-input signature register (MISR). The final content of the MISR is a signature that determines the pass/fail result. The signature is typically compared to a pre-calculated, or expected, signature.
A clock different than the clock used by the integrated circuit during normal, functional operation is typically used when in a test mode. In fact, BIST uses one test clock, and ATPG mode uses two separate test clocks.
Glitches can occur during the process of switching the integrated circuit over from the functional clock to one of the test clocks, or from one test clock to another test clock. Circuitry capable of generating the test clocks to be used, and capable of switching between the various clocks in a glitch free fashion, is therefore desirable.